ASIC Verification Engineers

We are hiring for multiple ASIC Verification Engineer to join a team that develops complex designs based in Sweden.

Educational Qualification: Bachelor of Engineering/M.Sc in Engineering or Equivalent.

Job Summary: 

• Engineer will be involved in new and existing ASIC projects working in teams.
• The team is currently working on a mix of IP design/verification and different level of SubSys integration/verification.

Required Experience / Competences:

• At least 3 years of experience in UVM.
• Good command on UVM verification and System Verilog.
• Should have worked with complex ASIC and/or large FPGA design.
• Experience from IP block verification, Multi clock domains, RTL within Verilog, VHDL and/or System Verilog.
• Meritorious in Test bench structuring and design, RTL design.
• Scripting skills, Lab experience, Telecommunication experience is essential.

Soft skills:

• Responsible and self-organized
• Able to prioritize the workload/tasks
• Quick learner and not afraid to face technical challenges
• Social and hold good team skills